1. Field of the Invention
The present invention relates to a memory device, and more specifically, it relates to a memory device such as a magnetic memory device including storage elements exhibiting a ferromagnetic tunnel effect or the like.
2. Description of the Background Art
An MRAM (magnetic random access memory), i.e., a nonvolatile memory recording data through magnetism, is known in general. This MRAM is disclosed in Nikkei Electronics, 1999. 11. 15 (No. 757), pp. 49-56 or the like in detail.
FIGS. 7 and 8 are schematic diagrams for illustrating the structure of a storage element 110 forming the MRAM disclosed in the aforementioned literature. Referring to FIG. 7, the storage element 110 of the conventional MRAM comprises a ferromagnetic layer 101, another ferromagnetic layer 103 and a non-magnetic layer 102 arranged between the ferromagnetic layers 101 and 103.
The ferromagnetic layer 101 is harder to invert than the ferromagnetic layer 103. The term xe2x80x9cferromagnetismxe2x80x9d denotes such magnetism that magnetic atoms or free atoms of a metal parallelly align magnetic moments due to positive exchange interaction for forming spontaneous magnetization, and a substance exhibiting such ferromagnetism is referred to as a ferromagnetic substance. The ferromagnetic layers 101 and 103 consist of such a ferromagnetic substance. In general, the non-magnetic layer 102 is formed by a GMR (giant magnetoresistance) film employing a metal. A TMR (tunneling magnetoresistance) film employing an insulator has recently been developed as the non-magnetic layer 102. The TMR film advantageously has larger resistance than the GMR film. More specifically, the MR ratio (resistance change) of the GMR film is on the 10% mark, while that of the TMR film is at least 20%. The storage element 110 consisting of the TMR film is hereinafter referred to as a TMR element 110.
The storage principle of the conventional MRAM employing the TMR element 110 is now described with reference to FIGS. 7 and 8. First, the state where the directions of magnetization of the two ferromagnetic layers 101 and 103 are identical to each other (parallel) is associated with data xe2x80x9c0xe2x80x9d, as shown in FIG. 7. The state where the directions of magnetization of the two ferromagnetic layers 101 and 103 are opposite to each other (antiparallel) is associated with data xe2x80x9c1xe2x80x9d, as shown in FIG. 8. The TMR element 110 exhibits small resistance (R0) when the directions of magnetization are parallel, while exhibiting large resistance (R1) when the directions of magnetization are antiparallel. The MRAM determines whether the data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d through the property of the TMR element 110 exhibiting different resistance values in response to the directions of magnetization.
FIG. 9 is a block diagram showing the overall structure of a conventional MRAM 150 having memory cells each formed by a single TMR element and a single transistor. The structure of the conventional MRAM 150 is now described with reference to FIG. 9.
A memory cell array 151 is formed by arranging a plurality of memory cells 120 in the form of a matrix (FIG. 9 shows only four memory cells 120, in order to simplify the illustration). Each memory cell 120 is formed by a single TMR element 110 and a single NMOS transistor 111.
In the memory cells 120 arranged in a row direction, the gates of the NMOS transistors 111 are connected to common read word lines RWL1 to RWLn. In the memory cells 120 arranged in the row direction, further, rewrite word lines WWL1 to WWLn are arranged on first ferromagnetic layers of the TMR elements 110.
In the memory cells 120 arranged in a column direction, first ferromagnetic layers of the TMR elements 110 are connected to common bit lines BL1 to BLn.
The read word lines RWL1 to RWLn are connected to a row decoder 152, and the bit lines BL1 to BLn are connected to a column decoder 153.
Externally specified row and column addresses are input in an address pin 154. The address pin 154 transfers the row and column addresses to an address latch 155. In the row and column addresses latched in the address latch 155, the row address is transferred to the row decoder 152 through an address buffer 156, and the column address is transferred to the column decoder 153 through the address buffer 156.
The row decoder 152 selects a read word line RWL corresponding to the row address latched in the address latch 155 from among the read word lines RWL1 to RWLn, while selecting a rewrite word line WWL corresponding to the row address latched in the address latch 155 from among the rewrite word lines WWL1 to WWLn. The row decoder 152 further controls the potentials of the read word lines RWL1 to RWLn and the rewrite word lines WWL1 to WWLn on the basis of a signal from a voltage control circuit 157.
The column decoder 153 selects a bit line BL corresponding to the column address latched in the address latch 155 from among the bit lines BL1 to BLn, while controlling the potentials of the bit lines BL1 to BLn on the basis of a signal from another voltage control circuit 158.
Externally specified data is input in a data pin 159. The data pin 159 transfers the data to the column decoder 153 through an input buffer 160. The column decoder 153 controls the potentials of the bit lines BL1 to BLn in correspondence to the data.
Data read from an arbitrary memory cell 120 is transferred from any of the bit lines BL1 to BLn to a sense amplifier group 161 through the column decoder 153. The sense amplifier group 161 is formed by current sense amplifiers. The data determined by the sense amplifier group 161 is output from an output buffer 162 through the data pin 159.
A control core circuit 163 controls the aforementioned operations of the circuits 152 to 162.
A write (rewrite) operation and a read operation of the conventional MRAM 150 having the aforementioned structure are now described.
(Write Operation)
In the write operation, the MRAM 150 feeds orthogonal currents to the selected rewrite word line WWL and the selected bit line BL. Thus, data can be rewritten only in the TMR element 110 located on the intersection between the rewrite word line WWL and the bit line BL. More specifically, the currents flowing through the rewrite word line WWL and the bit line BL form magnetic fields, so that the sum (composite field) of the two magnetic fields acts on the TMR element 110. The directions of magnetization of the TMR element 110 change from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d, for example, due to the composite field.
The remaining TMR elements 110 located on intersections excluding the aforementioned one include those fed with absolutely no currents and those fed with only unidirectional currents. In each TMR element 110 fed with no current, no magnetic fields are formed and hence the directions of magnetization remain unchanged. In each TMR element 110 fed with only a unidirectional current, formed magnetic fields are insufficient in strength for inverting the directions of magnetization. Therefore, the directions of magnetization remain unchanged also in the TMR element 110 fed with only a unidirectional current.
As hereinabove described, the MRAM 150 can write the directions of magnetization of the TMR element 110 located on the intersection between the selected bit line BL and the selected rewrite word line WWL as shown in FIG. 7 or 8 by feeding the currents to the bit line BL and the rewrite word line WWL corresponding to the selected address. Thus, the MRAM 150 can write data xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d.
(Read Operation)
In order to read the data written in the aforementioned manner, the MRAM 150 applies a voltage to the read word line RWL for rendering the NMOS transistor 111 conductive. In this state, the MRAM 150 determines whether the value of the current flowing through the bit line BL is larger or smaller than a reference current value, thereby determining xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
In the case of the data xe2x80x9c0xe2x80x9d shown in FIG. 7, the directions of magnetization are parallel and hence the TMR element 110 exhibits a small resistance value (R0). Therefore, the value of the current flowing through the bit line BL is larger than the reference current value. In the case of the data xe2x80x9c1xe2x80x9d shown in FIG. 8, on the contrary, the directions of magnetization are antiparallel and hence the TMR element 110 exhibits a larger resistance value (R1) than that in the case shown in FIG. 7. Therefore, the value of the current flowing through the bit line BL is smaller than the reference current value.
The aforementioned conventional MRAM 150 feeds the orthogonal currents to the selected rewrite word line WWL and the selected bit line BL in order to write data. If the TMR element 110 is refined, however, the directions of magnetization are so hard to invert that it is difficult to rewrite the data unless the values of the currents for writing are increased. Further, the conventional MRAM 150, which must feed a current every bit line in order to simultaneously rewrite data in the memory cells 120 connected to the selected rewrite word line WWL, requires currents in a number corresponding to the product of the current necessary for each memory cell 120 and the number of the bit lines BL1 to BLn. Thus, the MRAM 150 disadvantageously requires extremely large currents.
The MRAM 150 also requires rewrite currents in a number corresponding to the product of a rewrite cycle and the number of the bit lines BL1 to BLn in order to continuously rewrite data stored in the memory cells 120 connected with the selected rewrite word line WWL. Thus, the MRAM 150 requires large currents also in this case.
An object of the present invention is to provide a memory device capable of rewriting data with smaller current consumption as compared with a case of feeding a rewrite current every bit line.
Another object of the present invention is to easily connect current paths of first and second bit lines with each other in the aforementioned memory device.
In order to attain the aforementioned objects, a memory device according to a first aspect of the present invention comprises a first bit line and a second bit line having a current path independently of the first bit line, while rendering write current paths of the first bit line and the second bit line in common.
The memory device according to the first aspect can rewrite data with smaller current consumption as compared with a case of feeding a rewrite current every bit line by rendering the rewrite current paths of the first bit line and the second bit line having the current path independently of the first bit line in common as hereinabove described.
A memory device according to a second aspect of the present invention comprises a first bit line, a first pair line paired with the first bit line, a second bit line, a second pair line paired with the second bit line and a current path control circuit connecting either the first bit line or the first pair line and either the second bit line or the second pair line with each other in writing thereby connecting current paths of the first bit line and the second bit line with each other.
The memory device according to the second aspect is provided with the current path control circuit connecting either the first bit line or the first pair line and either the second bit line or the second pair line with each other in writing thereby connecting the current paths of the first bit line and the second bit line with each other as hereinabove described, to be capable of feeding a rewrite current to the first and second bit lines through a single current path in writing. Thus, the memory device can rewrite data with smaller current consumption as compared with the case of feeding a rewrite current every bit line.
The aforementioned memory device according to the second aspect preferably further comprises a first latch circuit for storing write data for the first bit line and a second latch circuit for storing write data for the second bit line, and connects the current path of the first bit line and the current path of the second bit line with each other on the basis of outputs from the first latch circuit and the second latch circuit. According to this structure, the memory device can easily connect the current paths of the first and second bit lines with each other through the first and second latch circuits.
In this case, the current path control circuit preferably includes a logic circuit operating on the basis of the outputs from the first latch circuit and the second latch circuit and a switching element on-off controlled on the basis of an output from the logic circuit. According to this structure, the memory device can easily connect the current paths of the first and second bit lines by on-off controlling the switching element. In this case, further, a write enable signal line may be connected to an input terminal of the logic circuit. According to this structure, the memory device can easily control the output of the logic circuit through the write enable signal line.
In the aforementioned memory device according to the second aspect, a memory cell including a storage element exhibiting a magnetoresistance effect is preferably connected to at least the first bit line and the second bit line. According to this structure, the memory device can write data in the memory cell including the storage element exhibiting a magnetoresistance effect by feeding a current to the first and second bit lines. In this case, the storage element exhibiting a magnetoresistance effect may include a TMR element exhibiting a ferromagnetic tunnel effect.
The aforementioned memory device having the memory cell including the storage element exhibiting a magnetoresistance effect preferably further comprises a plurality of word lines arranged to intersect with the first bit line, the first pair line, the second bit line and the second pair line and a plurality of auxiliary word lines provided in correspondence to the word lines respectively and connected with the memory cell, and performs a data write operation by feeding mutually intersecting currents to one of the auxiliary word lines and the first and second bit lines. According to this structure, the memory device can write data in the memory cell located on the intersection between the auxiliary word line and the first and second bit lines through a composite field of a magnetic field formed by the current flowing through the auxiliary word line and a magnetic field formed by the current flowing through the first and second bit lines.
The aforementioned memory device having the memory cell including the storage element exhibiting a magnetoresistance effect preferably connects the current path of the first bit line and the current path of the second bit line with each other so that currents oppositely flow through the first bit line and the second bit line when data written in a memory cell connected to the first bit line and a memory cell connected to the second bit line are different from each other. According to this structure, the memory device can easily write different data in the memory cells including the storage elements exhibiting a magnetoresistance effect. In this case, currents may oppositely flow through the first bit line and the first pair line, and currents may oppositely flow through the second bit line and the second pair line.
In the aforementioned memory device according to the second aspect, the first pair line preferably includes a first inverted bit line paired with the first bit line and supplied with a signal level complementary to the first bit line, and the second pair line preferably includes a second inverted bit line paired with the second bit line and supplied with a signal level complementary to the second bit line. According to this structure, the memory device can write data, reverse to those in memory cells connected with the first and second bit lines, in memory cells connected with the first and second inverted bit lines respectively by connecting the memory cells to the first and second inverted bit lines. In this case, a memory cell is preferably connected to the first bit line and the first inverted bit line, and another memory cell is preferably connected to the second bit line and the second inverted bit line.
In this case, each of the memory cells connected to the first bit line and the first inverted bit line and to the second bit line and the second inverted bit line may include two storage elements having a magnetoresistance effect and two transistors. Thus, the memory device can write data corresponding to the first and second bit lines in the first storage element of each memory cell while writing data corresponding to the first and second inverted bit lines in the second storage element.
In this case, the memory device preferably further comprises a first latch circuit for storing write data for the first bit line and a second latch circuit for storing write data for the second bit line, while the first and second latch circuits preferably include sense amplifiers. According to this structure, the memory device can use the first and second latch circuits also as sense amplifiers for determining read data in data reading.
In the aforementioned memory device according to the second aspect, the first pair line may include a first auxiliary bit line paired with the first bit line and connected with no memory cell, and the second pair line may include a second auxiliary bit line paired with the second bit line and connected with no memory cell. According to this structure, the memory device can easily connect the current paths of the first and second bit lines with each other through the first and second auxiliary bit lines. In this case, each of memory cells connected to the first bit line and to the second bit line may include a storage element having a magnetoresistance effect and a transistor. Further, the storage element exhibiting a magnetoresistance effect may include a TMR element exhibiting a ferromagnetic tunnel effect.
The aforementioned memory device including the first and second auxiliary bit lines preferably further comprises a reference bit line and an auxiliary reference bit line, while a reference memory cell including a resistance element and a transistor is preferably connected to the reference bit line. According to this structure, the memory device can easily determine data stored in the memory cell on the basis of resistance resulting from the resistance element of the reference memory cell and resistance resulting from the storage element of the memory cell exhibiting a magnetoresistance effect.
In this case, the memory device further comprises a first latch circuit for storing write data for the first bit line, a second latch circuit for storing write data for the second bit line and a sense amplifier connected with at least the reference bit line and provided independently of the first latch circuit and the second latch circuit. According to this structure, the memory device can store data to be written in the memory cell through the first and second latch circuits while determining the data written in the memory cell through the sense amplifier.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.